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| Discontinued - v3.0 ProASIC(R) 500K Family F ea t u re s an d B e n e fi t s H ig h C a p ac it y I/O * 100,000 to 475,000 System Gates * 14k to 63k Bits of Two-Port SRAM * 106 to 440 User I/Os P e r f o r m an c e * Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate * 3.3V, PCI Compliance (PCI Revision 2.2) S e c ur e P r o gr a m m in g The Industry's Most Effective Security Key Prevents Read Back of Programming Bit Stream S t a n da r d F P G A a nd A S I C D es ig n F lo w * 33 MHz PCI 32-bit PCI * Internal System Performance up to 250 MHz * External System Performance up to 100 MHz Lo w P ow e r * Low Impedance Flash Switches * Segmented Hierarchical Routing Structure * Small, Efficient Logic Cells H ig h P e r f o r m a nc e R o u t in g H ie r ar ch y * Flexibility with Choice of Industry-Standard Front-End Tools * Efficient Design Through Front-End Timing and Gate Optimization ISP Support * In-System Programming (ISP) with Silicon Sculptor and Flash Pro S R A M s a nd F I F O s * * * * Ultra Fast Local Network Efficient Long Line Network High Speed Very Long Line Network High Performance Global Network * Up to 150 MHz Synchronous and Asynchronous Operation * Netlist Generator Ensures Optimal Usage of Embedded Memory Blocks B o u nd a r y S c an T e st No nv o la t ile a n d Re pro g r am m a bl e Fl as h T e c hn o log y IEEE Std. 1149.1 (JTAG) Compliant * Live at Power Up * No Configuration Device Required * Retains Programmed Design During Power-Down/ Power-Up Cycles P ro A S I C P r o du c t P ro fi l e Device Maximum System Gates Typical Gates Maximum Flip-Flops Embedded RAM Bits Embedded RAM Blocks (256 X 9) Logic Tiles Global Routing Resources Maximum User I/Os JTAG PCI Package (by Pin Count) PQFP PBGA FBGA A500K050 100,000 43,000 5,376 14k 6 5,376 4 204 Yes Yes 208 272 144 A500K130 290,000 105,000 12,800 45k 20 12,800 4 306 Yes Yes 208 272, 456 144, 256 A500K180 370,000 150,000 18,432 54k 24 18,432 4 362 Yes Yes 208 456 256 A500K270 475,000 215,000 26,880 63k 28 26,880 4 440 Yes Yes 208 456 256, 676 February 2002 1 (c) 2002 Actel Corporation Pr oAS IC (R) 5 0 0 K F a m i l y G e n e ra l D e s cr i p t i o n The ProASIC 500K family's nonvolatile Flash technology combines the advantages of ASICs with the benefits of programmable devices. ProASIC 500K devices shorten time-to-production by enabling designers to create high-density systems using existing ASIC or FPGA design flows and tools. ASIC migration is not necessary for any volume because the family offers cost effective reprogrammable solutions, ideal for applications in the networking, telecom, computer, and consumer markets. The ProASIC 500K family consists of four devices ranging from 100k to 475k system gates and with up to 63k bits of O r d er i n g In f or m a t i o n A500K130 PQ 208 embedded two-port memory. These memory blocks include hardwired FIFO circuitry as well as circuits to generate or check parity. This minimizes external logic gate count and complexity while maximizing flexibility and utility. P r o c es s T ec h no lo g y The ProASIC 500K family achieves its nonvolatile and reprogrammability through an advanced 0.25, four-level metal LVCMOS process enhanced with Flash technology. The use of standard CMOS design techniques to implement logic and control functions results in highly predictable performance and gate array compatibility. Application (Ambient Temperature Range) Blank = Commercial (0 to +70 C) I = Industrial (-40 to +85 C) PP = Pre-production ES = Engineering Silicon (Room Temperature Only) Package Lead Count Package Type BG = Plastic Ball Grid Array PQ = Plastic Quad Flat Pack FG = Fine Ball Grid Array Part Number A500K050 = A500K130 = A500K180 = A500K270 = 100,000 Equivalent System Gates 290,000 Equivalent System Gates 370,000 Equivalent System Gates 475,000 Equivalent System Gates Note: This family has been discontinued. 2 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y P ro d u ct P l a n Application C A500K050 Device 144-Pin Fine Ball Grid Array (FBGA) 208-Pin Plastic Quad Flat Pack (PQFP) 272-Pin Plastic Ball Grid Array (PBGA) A500K130 Device 144-Pin Fine Ball Grid Array (FBGA) 208-Pin Plastic Quad Flat Pack (PQFP) 272-Pin Plastic Ball Grid Array (PBGA) 256-Pin Plastic Ball Grid Array (PBGA) 456-Pin Plastic Ball Grid Array (PBGA) A500K180 Device 208-Pin Plastic Quad Flat Pack (PQFP) 256-Pin Plastic Ball Grid Array (PBGA) 456-Pin Plastic Ball Grid Array (PBGA) A500K270 Device 208-Pin Plastic Quad Flat Pack (PQFP) 256-Pin Plastic Ball Grid Array (PBGA) 456-Pin Plastic Ball Grid Array (PBGA) 676-Pin Fine Ball Grid Array (FBGA) I Contact your Actel sales representative for package availability. Applications: C = Commercial Availability: = Available - Contact your Actel Sale's representative for the latest I = Industrial availability information. P l a s t i c D e v i c e R e s ou r c es User I/Os Device A500K050 A500K130 A500K180 A500K270 PQFP 208-Pin 164 164 164 164 PBGA 272-Pin 204 204 -- -- PBGA 456-Pin -- 306 362 362 FBGA 144-Pin 106 106 -- -- FBGA 256-Pin -- 192 192 192 FBGA 676-Pin -- -- -- 440 Package Definitions PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Ball Grid Array Discontinued - v3.0 3 Pr oAS IC (R) 5 0 0 K F a m i l y P ro A S I C 5 0 0 K A r c h i te c tu r e The ProASIC 500K family's proprietary architecture provides granularity comparable to gate arrays. Unlike SRAM-based FPGAs that utilize look-up tables or architectural mapping during design, ProASIC device designs are directly synthesized to gates. That streamlines the design flow, increases design productivity, and eliminates dependencies on vendor-specific design tools. The ProASIC 500K device core consists of a Sea-of-TilesTM(Figure 1), each of which can be configured as a 3-input logic function (e.g., NAND gate, D-Flip-Flop, etc.) by programming the appropriate Flash switch interconnections (See Figure 2 on page 5 and Figure 3 on page 5). Gates and larger functions are connected with four levels of routing hierarchy. Flash memory bits are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Flash switches are programmed to connect signal lines to the appropriate logic cell inputs and outputs. Dedicated high-performance lines are connected as needed for fast, low-skew global signal distribution throughout the core. Maximum core utilization is possible for virtually any design. The ProASIC 500K devices also contain embedded two-port SRAM blocks with built-in FIFO/RAM control logic. Programming options include synchronous or asynchronous operation, two-port RAM configurations, user defined depth and width, and parity generation or checking. Table 3 on page 12 lists the 24 basic memory configurations. F la sh S w it c h In the ProASIC Flash switch, two transistors share the floating gate which stores the programming information. One is the Flash transistor which stores programming information and in which erasing is performed. The second transistor connects/separates routing elements or configuration signal lines (Figure 2 on page 5). L og ic T ile The logic tile cell, Figure 3 on page 5, has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra fast local and efficient long line routing resources). Any three-input one-output logic function, except a three input XOR, can be configured as one tile. Two multiplexers with feedback paths through the NAND gates allow the tile to be configured as a latch with clear or set, or as a flip-flop with clear or set. Thus, the tiles can flexibly map logic and sequential gates of a design. 256x9 Two-Port SRAM or FIFO Block Logic Tile Figure 1 * The ProASIC Device Architecture 4 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y Sel 1 Sel 2 Floating Gate Switch In Word Switch Out Figure 2 * Flash Switch Local Routing In 1 Efficient Long Line Routing In 2 (CLK) In 3 (Reset) Figure 3 * Core Logic Tile Ro ut in g Re so u r ce s The routing structure of the ProASIC 500K devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra fast local resources, efficient long line resources, high speed very long line resources, and high performance global networks. The ultra fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight surrounding tiles (Figure 4 on page 6). The efficient long line resources provide routing for longer distances and higher fanout connections. These resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire ProASIC device (Figure 5 on page 6). Each tile can drive signals onto the efficient long line resources, while the resources can also access every input of any tile. The routing software automatically inserts active buffers to limit loading effects due to distance and fanout. The high speed very long line resources, spanning across the entire device with minimal delay, are used to route very long or very high fanout nets. These resources run vertically and horizontally, providing multiple access to each group of tiles throughout the device (Figure 6 on page 7). The high performance global networks' clock trees are low skew, high fanout nets that are accessible from four dedicated pins or from internal logic (Figure 7 on page 8). These nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. The global networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically, with signals accessing every input on all tiles. C l oc k R e s ou r c es ProASIC's high-drive routing structure provides four global networks, each accessible from either a dedicated global pad or a logic tile. Global lines provide optimized worst-case clock skew of 0.3ns. Discontinued - v3.0 5 Pr oAS IC (R) 5 0 0 K F a m i l y L L L L Inputs L Output L Ultra Fast Local Lines (connect a tile to the adjacent tile, I/O buffer, or memory block) L L L Figure 4 * Ultra Fast Local Resources 4 Tiles Long 2 Tiles Long 1 Tile Long L L L L Logic Tile L L L L L L L L L L L 1 Tile Long 2 Tiles Long 4 Tiles Long Figure 5 * Efficient Long Line Resources 6 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y Speed Very Long Line Resouces PAD RING I/O RING Figure 6 * High Speed Very Long Line Resources Discontinued - v3.0 7 Pr oAS IC (R) 5 0 0 K F a m i l y C lo c k T r e e s One of the main architectural benefits of ProASIC is the set of power and delay friendly global networks. The ProASIC family offers 4 global trees. Each of these trees is based on a network of spines and ribs that reach all the tiles in their regions (Figure 7). This flexible clock tree architecture allows users to map up to 56 different internal/external clocks in an A500K270 device (Table 1). The flexible use of the ProASIC clock spine allows the designer to cope with several design requirements. Users implementing clock resource intensive applications can easily route external or gated internal clocks using global routing spines. Users can also drastically reduce delay penalties and save buffering resources by mapping critical high fanout nets to spines. For design hints on using these features, refer to the Efficient Use of ProASIC Clock Trees application note. High Performace Global Network PAD RING PAD RING I/O RING Low Skew Global Networks Global Pads Global Pads Global Spine Global Ribs I/O RING Scope of Spine PAD RING Figure 7 * A500K130 Global Routing Resources Table 1 * Number of Clock Spines A500K050 Top Spine Height Tiles in Each Top Spine Bottom Spine Height Tiles in Each Bottom Spine Global Clock Networks (Trees) Clock Spines/Tree Total Spines Total Tiles 24 768 32 1,024 4 6 24 5,376 A500K130 32 1,024 40 1,280 4 10 40 12,800 A500K180 40 1,280 56 1,792 4 12 48 18,432 A500K270 56 1,792 64 2,048 4 14 56 26,880 8 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y I n pu t / O ut pu t B lo ck s To meet complex system design needs, the ProASIC 500K family offers devices with a large number of I/O pins, up to 440 user I/O pins on the A500K270. If the I/O pad is powered at 3.3V, each I/O can be selectively configured at 2.5V and 3.3V threshold levels. Table 2 shows the available supply voltage configurations. Figure 8 illustrates I/O interfaces with other devices. Table 2 * ProASIC Power Supply Voltages VDDP Input Tolerance Output Drive Note: VDDL is always 2.5V. 2.5V 2.5V 2.5V 3.3V 3.3V, 2.5V 3.3V, 2.5V All I/Os also include an ESD protection circuit. Each I/O is tested according to the following model: * Human Body Model (HBM) (Per Mil Std 883 Method 3015) 2000V 2.5V Device ProASIC VDDL = 2.5V VDDP = 2.5V 2.5V Device 2.5V Device ProASIC VDDL = 2.5V VDDP = 3.3V 3.3V Device 2.5V Device 3.3V Device The I/O pads are fully configurable to provide the maximum flexibility and speed. Each pad can be configured as an input, an output, a three-state driver, or a bidirectional buffer (Figure 9). I/O pads configured as inputs have the following features: * Individually selectable 2.5V or 3.3V threshold levels1 * Optional pull-up resistor I/O pads configured as outputs have the following features: * Individually selectable 2.5V or 3.3V compliant output signals1 * 3.3V PCI compliant * Ability to drive LVTTL and LVCMOS levels * Selectable drive strengths * Selectable slew rates * Tristate I/O pads configured as bidirectional buffers have the following features: * Individually selectable 2.5V or 3.3V compliant output signals and threshold levels1 * 3.3V PCI compliant * Optional pull-up resistor * Selectable drive strengths * Selectable slew rates * Tristate Figure 8 * I/O Interfaces 3.3V/2.5V Signal Control Pull-up Control Y EN Pad A 3.3V/2.5V Signal Control Drive Strength and Slew Rate Control Figure 9 * I/O Block Schematic Representation B o u nd a r y S c an ProASIC devices are compatible with IEEE Standard 1149.1, which defines a set of hardware architecture and mechanisms for cost-effective board-level testing. The basic ProASIC boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data registers, and instruction register (Figure 10 on page 10). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and BYPASS), the optional IDCODE instructions and private instructions used for device programming and factory testing. Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI and TDO (test data input and output), TMS (test mode selector) and TRST (test reset input). TMS, TDI, and TRST are equipped 1. If pads are configured for 2.5V operation, they are compliant with 2.5V level signals as defined by JEDEC JESD 8-5. If pads are configured for 3.3V operation, they are compliant to the standard as defined by JEDEC JESD 8-A (LVTTL and LVCMOS). Discontinued - v3.0 9 Pr oAS IC (R) 5 0 0 K F a m i l y with pull-up resistors to ensure proper operation when no input data is supplied to them. These pins are dedicated for boundary-scan test usage. The TAP controller is a four-bit state machine (16 states) that operates as shown in Figure 11 on page 11. The `1's and `0's represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles. The TRST pin may also be used to asynchronously place the TAP controller in the Test-Logic-Reset state. ProASIC devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device; this speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four fields (LSB, ID number, part number and version). The boundary-scan register observes and controls the state of each I/O pin. Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary scan register chain which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O. Details on the implementation of boundary-scan testing on ProASIC devices can be found in the Actel application note, Using JTAG Boundary-Scan with ProASIC Devices. I/O I/O I/O I/O I/O Test Data Registers Figure 10 * ProASIC JTAG Boundary Scan Test Logic Circuit 10 Discontinued - v3.0 O I/O Instruction TAP Controller Register Device Logic I/O I/O Bypass Register Pr oAS IC (R) 5 0 0 K F a m i l y Select-DRScan 0 1 Select-IRScan 1 0 Figure 11 * TAP Controller State Diagram User Security E m b e dd e d M e m o r y C o nf ig ur a t io n s The ProASIC 500K devices have read-protect bits that, once programmed, lock the entire programmed contents from being read externally. The user can only reprogram the device using the security key. This protects it from being read back and duplicated. Since programmed data is stored in nonvolatile Flash cells (which act like very small capacitors), rather than in the wiring, physical deconstruction cannot be used to compromise data. That approach would be further hampered by the placement of the flash cells, beneath the four metal layers (whose removal could not be accomplished without disturbing the charge on the floating gate). This is the highest security provided in the industry. For more information, refer to the Design Security for Nonvolatile Flash and Antifuse FPGAs white paper for more information. E m b ed d ed M e m or y F lo o r pl an The embedded memory in the ProASIC 500K family provides great configuration flexibility. While other programmable vendors typically use single port memories that can only be transformed into two-port memories by sacrificing half the memory, each ProASIC block is designed and optimized as a two-port memory (1 read, 1 write). This provides 63k bits of total memory for two-port and single port usage in the A500K270 device. Each memory can be configured as FIFO or SRAM, with independent selection of synchronous or asynchronous read and write ports (Table 3 on page 12). Multiple write ports are not supported. Additional characteristics include programmable flags as well as parity check and generation. Figure 12 and Figure 13 on page 13 show the block diagrams of the basic SRAM and FIFO blocks. These memories are designed to operate up to 133 MHz when operated individually. Each block contains a 256 word deep by 9-bit wide (1 read, 1 write) memory. The memory blocks may be combined in parallel to form wider memories or stacked to form deeper memories (Figure 14 on page 14). This provides optimal bit widths of 9 (1 block), 18, 36, and 72, and optimal depths of 256, 512, 768, and 1024. Refer to the Macro Library Guide for more information. The embedded memory is located across the top of the device (see Figure 1 on page 4) in 256x9 blocks. Depending upon the device, 6 to 28 blocks are available to support a variety of memory configurations. Each block can be programmed as an independent memory or combined (using dedicated memory routing resources) to form larger, more complex memories. Discontinued - v3.0 11 Pr oAS IC (R) 5 0 0 K F a m i l y Figure 15 on page 14 gives an example of optimal memory usage. Ten blocks with 23,040 bits have been used to generate three memories of various widths and depths. Figure 16 on page 14 shows how memory can be doubled up to create extra read ports. In this example, 10 out of 28 Table 3 * Basic Memory Configurations Type RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO Write Access Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Read Access Asynchronous Asynchronous Synchronous Transparent Synchronous Transparent Synchronous Pipelined Synchronous Pipelined Asynchronous Asynchronous Synchronous Transparent Synchronous Transparent Synchronous Pipelined Synchronous Pipelined Asynchronous Asynchronous Synchronous Transparent Synchronous Transparent Synchronous Pipelined Synchronous Pipelined Asynchronous Asynchronous Synchronous Transparent Synchronous Transparent Synchronous Pipelined Synchronous Pipelined blocks of the A500K270 yield an effective 6,912 bits of multiple port memories. The ACTgenTM software facilitates building wider and deeper memories for optimal memory usage. Parity Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Library Cell Name RAM256x9AA RAM256x9AAP RAM256xAST RAM256xASTP RAM256x9ASR RAM256x9ASRP RAM256x9SA RAM256xSAP RAM256x9SST RAM256x9SSTP RAM256x9SSR RAM256x9SSRP FIFO256xAA FIFO256x9AAP FIFO256xAST FIFO256x9ASTP FIFO256x9ASR FIFO256x9ASRP FIFO256x9SA FIFO256xSAP FIFO256x9SST FIFO256x9SSTP FIFO256x9SSR FIFO256x9SSRP 12 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y DI <0:8> WADDR <0:7> WRB WBLKB WCLKS WPE SRAM (256 X 9) Sync Write & Sync Read Ports DO <0:8> RADDR <0:7> RDB RBLKB RCLKS RPE DI <0:8> WADDR <0:7> WRB SRAM (256 X 9) Async Write & Async Read Ports DO <0:8> RADDR <0:7> RDB RBLKB RPE WBLKB WPE PARODD PARODD DI <0:8> WADDR <0:7> WRB WBLKB WCLKS WPE SRAM (256 X 9) Sync Write & Async Read Ports DO <0:8> RADDR <0:7> RDB RBLKB DI <0:8> WADDR <0:7> WRB WBLKB DO <0:8> SRAM (256 X 9) Async Write & Sync Read Ports RADDR <0:7> RDB RBLKB RCLKS RPE RPE WPE PARODD PARODD Note: For memory block interface signal definitions, see Table 4 on page 28. Figure 12 * Example SRAM Block Diagrams D1<0:8> LEVEL<0:7> LGDEP<0:2> WRB WBLKB RDB RBLKB PARODD WCLKS RCLKS FIFO (256 X 9) Sync Write & Sync Read Ports WPE RPE FULL EMPTY EQTH GEQTH D0 <0:8> D1 <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB D0 <0:8> RDB RBLKB PARODD WCLKS FIFO (256 X 9) Sync Write & Async Read Ports WPE RPE FULL EMPTY EQTH GEQTH RESET D1 <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB D0 <0:8> D1 <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB D0 <0:8> RDB RBLKB PARODD FIFO (256 X 9) Async Write & Sync Read Ports WPE RPE FULL EMPTY EQTH GEQTH RDB RBLKB FIFO (256 X 9) Async Write & Async.Read Ports WPE RPE FULL EMPTY EQTH GEQTH PARODD RCLKS Note: For memory block FIFO signal definitions, see Table 5 on page 34. Figure 13 * Basic FIFO Block Diagrams Discontinued - v3.0 13 Pr oAS IC (R) 5 0 0 K F a m i l y 9 Word Width 9 9 9 9 9 9 Word Depth 256 256 256 256 9 256 256 256 256 256 9 ... 88 blocks Figure 14 * A500K270 Memory Block Architecture Word Width 9 Word 256 Depth 256 9 256 256 9 9 256 256 words x 18bits, 1 read, 1 write 9 256 512 words x 18bits, 1 read, 1 write 256 1,024 words x 9bits, 1 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 23,040 Figure 15 * Example Showing Memories with Different Widths and Depths Word Width 9 Word Depth 256 9 Write Port 9 256 9 Write Port Read Ports 256 words x 9bits, 2 read, 1 write Read Ports 512 words x 9bits, 4 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 6,912 Figure 16 * Multiport Memory Usage 14 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y D e s i g n E n v i r o n m e nt ProASIC devices are supported by Actel's Designer Series software, as well as all of the industry standard third party CAE tools. Unlike other FPGA vendors, no special HDL instantiation or device related attributes are needed when using the standard VHDL or Verilog HDL design flow with ProASIC. As a result, designers can utilize the technology independent of HDL code for ProASIC devices. This feature and the ASIC-like design flow ensure a seamless transition to an ASIC implementation, if production volumes warrant a migration to a gate array or a standard cell product (Figure 17). ACTgen automatically generates memories and FIFOs with all the various options (width, depth, access mode, parity checking or generation, flags, etc.). For a synchronous read port, the user can choose whether the output is pipelined or transparent. ACTgen allows any bit width up to 252 (for the A500K270 device). ACTgen also enables optimal memory stacking in 256-word increments. However, any word depth may be combined for up to 7,168 words. ACTgen allows the user to generate distributed memory. Place and route is performed by Actel's Designer software. Available for UNIX workstations and PC platforms, Designer software accepts standard netlists in Verilog, VHDL, and in EDIF format, performs timing driven place and route of the design into the selected device/package, and provides postlayout timing information for backannotated simulation or static timing analysis. The Designer software also contains very powerful layout capabilities for the experienced user. A very comprehensive set of floor planning, timing, and routing constraints gives users optimal control over the tools' capabilities, enabling them to meet their tight design requirements. Users have access to constraints that allow them full control of the resources management. See the Designer User's Guide for various constraints and their uses. The ProASIC devices are also fully supported by Actel's Libero design tool suite. Libero is a design management environment that integrates the needed design tools, streamlines the design flow, manages all design and log files, and passes the necessary design data between tools. Libero includes Synplify, ViewDraw, Actel's Designer Series, ModelSim HDL Simulator, and WaveFormer Lite. Once the design is finalized, the programming bitstream is downloaded into the device programmer for ProASIC part programming. ProASIC 500K devices can be programmed with the Silicon Sculptor II and Flash Pro programmers. On-board programming is also available. Refer to the In-System Programming ProASIC 500K with Silicon Sculptor application note for more information. Design Creation/Verification High-Level Design (Verilog or VHDL) Synthesis Tool Verilog or VHDL Simulator Synthesis Library Simulation Library Forward Constraints Structural Netlist Design Implementation P&R User Constraints Designer (P&R Tool) Backannotation ACTgen Programming Programming Data Timing and Simulation SDF Timing File Silicon Sculptor II Timing Libraries Simulation Library Flash Pro Verilog or VHDL Simulator Timing Analyzer Figure 17 * ProASIC Design Flow Discontinued - v3.0 15 Pr oAS IC (R) 5 0 0 K F a m i l y P ac k a g e Th e r m a l C h a ra c t er i s ti c s The ProASIC 500K family is available in a number of package types. Actel has selected packages based on high pin count, reliability factors, and superior thermal characteristics. Thermal resistance indicates the ability of a package to conduct heat away from the silicon, through the package, to the surrounding air. Junction-to-ambient thermal resistance is measured in degrees Celsius/Watt and is represented as Theta ja (ja). The lower the thermal resistance, the more efficiently a package will dissipate heat. A package's maximum allowed power (P) is a function of maximum junction temperature (TJ), maximum ambient Package Type Plastic Quad Flat Pack (PQFP) PQFP with Heatspreader Plastic Ball Grid Array (PBGA) Plastic Ball Grid Array (PBGA) Fine Ball Grid Array (FBGA) Fine Ball Grid Array (FBGA) Pin Count 208 208 272 456 144 256 operating temperature (TA), and junction-to-ambient thermal resistance ja. Maximum junction temperature is the maximum allowable temperature on the active surface of the IC and is 110 C. P is defined as: TJ - TA P = --------------- ja ja is a function of the rate (in linear feet per minute - lfpm) of airflow in contact with the package. When the estimated power consumption exceeds the maximum allowed power, other means of cooling, such as increasing the airflow rate, must be used. jc 8 3.8 3 3 3.8 3.0 ja Still Air 30 20 20 18 38.8 30 ja 300 ft/min 23 17 16.5 14.5 26.7 25 Units C/W C/W C/W C/W C/W C/W 16 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y C a l c u l at i n g P o w er D i s s i pa t i o n Pmemory = P6 * Nmem * Fmem where: = 100.0 uW/MHz is the average power consumption of a memory block normalized per MHz of the clock Nmem = the number of RAM/FIFO blocks (1 block = 256 words * 9 bits) Fmem = the clock frequency of the memory The following is an example using a shift register design with 13,440 storage tiles and 0 logic tile. This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz for a A500K270. Fs = 10 MHz s = 13,440 => Pclock = (P1 + P2 * s) * Fs = 159.4 mW ms = 13,440 (in a shift register 100% of storage-tiles are toggling at each clock cycle and Fs = 10 MHz => Pstorage = P5 * ms * Fs = 134.4 mW mc = 0 (no logic tile in this shift-register) => Fp = 5 MHz Cload = 40 pF VDDP = 3.3 V and p = 24 => => Pios = (P4 + Cload * Vddp^2) * p * Fp = 54.1 mW Pmemory = 0 mW Nmem = 0 (no RAM/FIFO in this shift-register) * Pac = Pclock + Pstorage + Plogic + Pios + Pmemory = 347.9 mW * Pdc = 10 mW * Ptotal = Pdc + Pac = 357.9 mW Po w e r Co n su m p t io n of a 50 0 K D ev ic e 1000 Power Consumption (mW) ProASIC device power is calculated with both a static and an active component. The active component is a function of both the number of tiles utilized and the system speed. Power dissipation can be calculated using the following formula: Ptotal = Pdc + Pac where: Pdc = 10 mW Pac = Pclock + Pstorage + Plogic + Pios + Pmemory Pclock = (P1 + P2 * s) * Fs where: P1 = 2500 uW/MHz the basic power consumption of the clock-tree normalized per MHz of the clock P2 = 1.0 uW/MHz the extra power consumption of the clock-tree per storage-tile normalized per MHz of the clock s = the number of storage tiles clocked by this clock Fs = the clock frequency Pstorage = P5 * ms * Fs where: P5 = 1.0 uW/MHz the average power consumption of a storage-tile normalized per MHz of its output ms = the number of storage tiles switching at each Fs cycle Fs = the clock frequency Plogic = P3 * mc * Fs where: P3 = 3.0 uW/MHz the average power consumption of a logic-tile normalized per MHz of its output mc = the number of logic tiles switching at each Fs cycle Fs = the clock frequency Pios = (P4 + Cload * Vddp^2) * p * Fp where: P4 = 15.0 uW/MHz the average power consumption of an output-pad normalized per MHz of its output (internal powerload is not included) Cload = the output load p = the number of outputs Fp = the average output frequency P6 Plogic = 0 mW 900 800 700 600 500 400 300 200 100 0 ProASIC PLUS 110 instances of 16-bit binary counters 20 30 40 50 60 70 80 90 100 120 Frequency (MHz) Discontinued - v3.0 17 Pr oAS IC (R) 5 0 0 K F a m i l y O p e ra t i n g C o nd i t i o n s A b s ol ut e M a xi m um R at i ng s Parameter Supply Voltage Core (VDDL) Supply Voltage I/O Ring (VDDP) DC Input Voltage PCI DC Input Voltage DC Input Clamp Current Note: Condition Minimum -0.3 -0.3 -0.3 -0.5 Maximum 3.0 4.0 VDDP + 0.3 VDDP + 0.5 +10 Units V V V V mA VIN < 0 or VIN> VDDP -10 Stresses beyond those listed in the Absolute Maximum Ratings table can cause permanent damage to the device. Exposure to maximum rated conditions for extended periods can adversely affect device reliability. Operation of the device at these conditions or any others beyond those listed in the Recommended Operating Conditions is not implied. P r o g r am m in g a nd S t or a g e T e m pe r a t ur e L I m i t s Storage Temperature Product Grade Commercial Industrial S u p pl y V o lt a ge s Programming Cycles 50 50 Program Retention 20 years 20 years Min. -55C -55C Max. 110C 110C Mode Single Voltage Mixed Voltage VDDL 2.5V 2.5V VDDP 2.5V 3.3V VPP 2.5V Vpp 16.5V 3.3V Vpp 16.5V VPN -12V VPN 0V -12V VPN 0V Re co m m en d ed O pe r a t in g Co nd iti on s Parameter Commercial DC Supply Voltage (2.5V I/Os) DC Supply Voltage (Mixed 2.5V and 3.3V I/Os) Operating Ambient Temperature Range Maximum Operating Junction Temperature Maximum Clock Frequency Maximum RAM Frequency Industrial DC Supply Voltage (2.5V I/Os) DC Supply Voltage (Mixed 2.5V and 3.3V I/Os) Operating Ambient Temperature Range Maximum Operating Junction Temperature Maximum Clock Frequency Maximum RAM Frequency Symbol Limits VDDL & VDDP VDDP VDDL TA TJ fCLOCK fRAM VDDL & VDDP VDDP VDDL TA TJ fCLOCK fRAM 2.3V to 2.7V 3.0V to 3.6V 2.3V to 2.7V 0C to 70C 110C 250 MHz 150 MHz 2.3V to 2.7V 3.0V to 3.6V 2.3V to 2.7V -40C to 85C 110C 250 MHz 150 MHz 18 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y D C E l e c t r i c a l S p e c i f i ca t i o n s ( V D DP = 2. 5V ) Symbol Parameter Conditions Min. 2.3 Typ. Max. 2.7 Units V VDDP, VDDL Supply Voltage Output High Voltage High Drive (OB25LPH) VOH Low Drive (OB25LPL) IOH = -2.0 mA IOH = -4.0 mA IOH = -8.0 mA IOH = -1.0 mA IOH = -2.0 mA IOH = -4.0 mA IOL = 5.0 mA IOL = 10.0 mA IOL = 15.0 mA IOL = 2.0 mA IOL = 3.5 mA IOL = 5.0 mA 2.1 2.0 1.7 2.1 2.0 1.7 0.2 0.4 0.7 0.2 0.4 0.7 1.7 -0.3 VDDP + 0.3 0.7 250 10 4.0 10 10 120 100 100 30 10 10 V Output Low Voltage High Drive (OB25LPH) VOL Low Drive (OB25LPL) V VIH VIL Input High Voltage Input Low Voltage Input Current Quiescent Supply Current 3-State Output Leakage Current Output Short Circuit Current High 2 V V A A mA A IIN2 IDDQ IOZ with pull-up without pull-up VIN = VSS3 or VDDL VOH = VSS or VDDL VIN = VSS VIN = VSS VIN = VDDP VIN = VDDP 25 IOSH High Drive (OB25LPH) Low Drive (OB25LPL) Output Short Circuit Current Low mA IOSL CI/O CCLK High Drive (OB25LPH) Low Drive (OB25LPL) I/O Pad Capacitance Clock Input Pad Capacitance mA pF pF Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. Current is negative. 3. No pull-up resistor. Discontinued - v3.0 19 Pr oAS IC (R) 5 0 0 K F a m i l y D C E l e c t r i c a l S pe c i f i ca t i o n s ( V D DP = 3. 3V ) Symbol VDDP VDDL Parameter Supply Voltage Supply Voltage, Logic Array Output High Voltage 3.3V I/O, High Drive (OB33P) Conditions Min. 3.0 2.3 Typ. Max. 3.6 2.7 Units V V IOH = -5.0 mA IOH = -10.0 mA IOH = -2.5 mA IOH = -5.0 mA IOH = -200A IOH = -10.0 mA IOH = -2.0 mA IOH = -100A IOH = -1.0 mA IOH = -2.0 mA IOL = 7.5 mA IOL = 12.0 mA IOL = 4.0 mA IOL = 5.0 mA IOL = 5.0 mA IOL = 12.0 mA IOL = 16.0 mA IOL = 2.5 mA IOL = 5.0 mA IOL = 8.0 mA 0.9VDDP 2.4 V 0.9VDDP 2.4 2.1 2.0 1.7 V 2.1 2.0 1.7 0.1VDDP 0.4 V 0.1VDDP 0.4 0.2 0.4 0.7 V 0.2 0.4 0.7 2 1.7 -0.3 -0.3 VDDP + 0.3 VDDP + 0.3 0.8 0.7 300 10 4.0 70 10 400 10 V 3.3V I/O, Low Drive (OB33L) VOH Output High Voltage 2.5V I/O, High Drive (OB25H) 2.5V I/O, Low Drive (OB25L) Output High Voltage 3.3V I/O, High Drive (OB33P) 3.3V I/O, Low Drive (OB33L) VOL Output High Voltage 2.5V I/O, High Drive (OB25H) 2.5V I/O, Low Drive (OB25L) Input High Voltage 3.3V LVTTL/LVCMOS 2.5V Mode Input Low Voltage 3.3V LVTTL/LVCMOS 2.5V Mode Input Current LVTTL/LVCMOS LVTTL/LVCMOS Quiescent Supply Current Incremental Quiescent Supply Current 3-State Output Leakage Current VIH VIL V A A mA A A IIN2 IDDQ IDDQI4 IOZ with pull-up without pull-up VIN = VSS3 or VDDL 30 VOH = VSS or VDDL Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. Current is negative. 3. No pull-up resistor. 4. IDDQ is augmented by IDDQI for each 2.5V I/O when operating in a mixed voltage environment. 20 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y D C E l e c t r i c a l S p e c i f i ca t i o n s ( V D DP = 3. 3V ) ( C o nti nu e d) Symbol Parameter Output Short Circuit Current High 3.3V High Drive 3.3 Low Drive 2.5V High Drive 2.5 Low Drive Output Short Circuit Current Low 3.3V High Drive 3.3 Low Drive 2.5V High Drive 2.5 Low Drive Conditions Min. Typ. Max. 200 140 Units IOSH 2 mA 120 100 160 150 mA 160 50 10 10 pF pF IOSL CI/O I/O Pad Capacitance CCLK Clock Input Pad Capacitance Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. Current is negative. 3. No pull-up resistor. 4. IDDQ is augmented by IDDQI for each 2.5V I/O when operating in a mixed voltage environment. D C S p e ci f i c a t i o n s ( 3. 3V PC I O pe r a t i o n) Symbol VDDL VDDP VIH VIL IIPU IIL VOH VOL CIN CCLK Parameter Supply Voltage for Core Supply Voltage for I/O Ring Input High Voltage Input Low Voltage Input Pull-up Voltage1 Current2 Condition Min. 2.3 3.0 0.5VDPP -0.5 0.7VDDP Max. 2.7 3.6 VDPP + 0.5 0.3VDDP +10 Units V V V V V A V Input Leakage 0 < VIN < VCCI IOUT = -500 A IOUT = 1500 A -10 0.9VDPP Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance 3 0.1VDPP 10 5 12 V pF pF Notes: 1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this input voltage. 2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK). Discontinued - v3.0 21 Pr oAS IC (R) 5 0 0 K F a m i l y A C S p e ci f ic a t io n s ( 3. 3V PC I O pe r a t i o n ) Symbol Parameter Condition 0 < VOUT 0.3VCCI 1 Min. -12VCCI 1 Max. Units mA mA Switching Current High IOH(AC) (Test Point) 0.3VCCI VOUT < 0.9VCCI 0.7VCCI < VOUT < VCCI 1, 2 VOUT = 0.7VCC 2 VCCI > VOUT 0.6VCCI 1 (-17.1 + (VDDP - VOUT)) Equation A on page 23 -32VCCI 16VDDP (26.7VOUT) Equation B on page 23 38VCCI -25 + (VIN + 1)/0.015 25 + (VIN - VDDP - 1)/0.015 1 1 4 4 mA mA mA Switching Current Low IOL(AC) (Test Point) ICL ICH slewR slewF Low Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate 0.6VCCI > VOUT > 0.1VCCI 1 0.18VCCI > VOUT > 0 1, 2 VOUT = 0.18VCC 2 -3 < VIN -1 VCCI + 4 > VIN VCCI + 1 0.2VCCI to 0.6VCCI load 0.6VCCI to 0.2VCCI load 3 3 mA mA mA V/ns V/ns Notes: 1. Refer to the V/I curves in Figure 18 on page 23. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are system outputs. "Switching Current High" specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain outputs. 2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B) are provided with the respective diagrams in Figure 18 on page 23. The equation defined maxima should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs. pin output buffer 10 pF 1k 1/2 in. max. pin output buffer 1k 10 pF 22 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y Figure 18 shows the 3.3V PCI V/I curve and the minimum and maximum PCI drive characteristics of the ProASIC family. 150.0 IOL MAX Spec 100.0 IOL Current (mA) 50.0 0.0 0 -50.0 -100.0 -150.0 Voltage Out (V) IOH IOL MIN Spec IOH MIN Spec 0.5 1 1.5 2 2.5 3 3.5 4 IOH MAX Spec Figure 18 * 3.3V PCI V/I Curve for ProASIC Family Equation A IOH = (98.0/VCCI) * (VOUT - VCCI) * (VOUT + 0.4VCCI) for 0.7 VCCI < VOUT < VCCI T i m i n g C h a ra c t er i s ti c s Equation B IOL = (256/VCCI) * VOUT * (VCCI - VOUT) for 0V < VOUT < 0.18 VCCI Timing characteristics for ProASIC 500K devices fall into three categories: family dependent, device dependent, and design-dependent. The input and output buffer characteristics are common to all ProASIC 500K family members. Internal routing delays are device-dependent. Design dependency means that actual delays are not determined until after placement and routing of the user's design are completed. Design timing attributes may then be determined by using Timer, the Static Analysis tool embedded into Designer software, or performing simulation with post-layout delays using ModelSim Simulator integrated into Libero design environment. C r i t ic al N e t s a nd T yp ic a l N e t s V e r y L on g L in es Some nets in the design are very long lines marked using VLLs, which are special routing resources that span multiple rows, columns, or modules. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6 percent of nets in a fully utilized device require long tracks. Very long lines contribute between 4 and 8.4ns routing delay depending on the fanout. This additional delay is represented statistically in higher fanout routing delays. Timing Derating Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most critical timing paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6 percent of the nets in a design may be designated as critical, while more than 90% of the nets in a design are typical. User's can control priorities between critical nets and use routing constraints, such as set_critical to focus the routing optimization on the most critical ones. Please see the Designer User's Guide for more information on using constraints. Since ProASIC 500K devices are manufactured with a CMOS process, device performance will vary with temperature, voltage, and process. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and optimal process variations. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case process variations (within process specifications). Discontinued - v3.0 23 Pr oAS IC (R) 5 0 0 K F a m i l y T em p er a tu r e an d V o l t a ge D er a ti ng F a c to r s ( N o r m a l i z e d t o W o r s t -C as e C o m m er c i a l , T J = 70 C , V C CA = 2. 3V ) Junction Temperature (TJ) VCCA 2.3V 2.5V 2.7V -55C 0.84 0.81 0.77 -40C 0.86 0.83 0.79 0C 0.91 0.87 0.84 25C 0.94 0.90 0.86 70C 1.00 0.96 0.92 85C 1.02 0.98 0.93 110C 1.05 1.01 0.96 125C 1.07 1.02 0.98 Sl ew R at es M e as u r e d at C o u t = 1 0 pF ( T o t a l O u t p ut Lo a d) , N om in a l P ow e r S up p lie s a nd 2 5 C Type Trig. Lev. Rising Edge pS Slew Rate V/nS 3.33 2.85 2.33 2.83 2.13 1.62 1.33 1.18 0.76 1.26 1.15 0.78 2.13 1.81 1.30 1.68 1.15 0.87 Falling Edge pS 390 450 527 700 767 1100 310 390 510 430 730 1037 433 527 753 707 760 1563 Slew Rate V/nS -3.38 -2.93 -2.51 -1.89 -1.72 -1.20 -3.23 -2.56 -1.96 -2.33 -1.37 -0.96 -2.31 -1.90 -1.33 -1.42 -1.32 -0.54 OB33PH OB33PN OB33PL OB33LH OB33LN OB33LL OB25HH OB25HN OB25HL OB25LH OB25LN OB25LL OB25LPHH OB25LPHN OB25LPHL OB25LPLH OB25LPLN OB25LPLL 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 397 463 567 467 620 813 750 850 1310 793 870 1287 470 533 770 597 873 1153 T ri s t at e B u ff e r D el ay s EN A OTBx PAD A PAD VOL 50% 50% VOH 50% 50% EN PAD 50% VCC 50% 50% VOL 10% EN PAD GND 50% 50% VOH 50% 90% tDLH tDHL tENZL tENZH 24 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y T r i s t a t e B uf f e r D e l a y s ( W o r st - C a se C om m e r ci al C o nd it io ns , V DDP = 3 .0 V , V D DL = 2 .3 V , T J = 70 C, f C L O CK = 25 0 M H z ) Macro Type OTB33PH OTB33PN OTB33PL OTB33LH OTB33LN OTB33LL OTB25HH OTB25HN OTB25HL OTB25LH OTB25LN OTB25LL OTB25LPHH OTB25LPHN OTB25LPHL OTB25LPLH OTB25LPLN OTB25LPLL Description 3.3V, PCI Output Current, High Slew Rate 3.3V, PCI Output Current, Nominal Slew Rate 3.3V, PCI Output Current, Low Slew Rate 3.3V, Low Output Current, High Slew Rate 3.3V, Low Output Current, Nominal Slew Rate 3.3V, Low Output Current, Low Slew Rate 2.5V, High Output Current, High Slew Rate 2.5V, High Output Current, Nominal Slew Rate 2.5V, High Output Current, Low Slew Rate 2.5V, Low Output Current, High Slew Rate 2.5V, Low Output Current, Nominal Slew Rate 2.5V, Low Output Current, Low Slew Rate 2.5V, Low Power, High Output Current, High Slew Rate 2.5V, Low Power, High Output Current, Nominal Slew Rate 2.5V, Low Power, High Output Current, Low Slew Rate 2.5V, Low Power, Low Output Current, High Slew Rate 2.5V, Low Power, Low Output Current, Nominal Slew Rate 2.5V, Low Power, Low Output Current, Low Slew Rate Max tDLH 4.2 4.7 5.3 6.0 6.7 7.5 6.9 7.2 8.2 10.4 11.0 11.9 5.1 6.0 6.9 7.4 8.6 9.8 Max tDHL 4.1 5.9 7.0 6.6 9.2 12.0 3.6 5.2 6.4 5.5 8.3 10.9 5.1 7.7 9.8 8.6 12.6 17.0 Max tENZH 4.2 4.8 5.3 6.0 6.7 7.5 6.9 7.2 8.2 10.4 11.0 11.9 5.1 6.0 6.8 7.4 8.5 9.8 Max tENZL 3.67 5.3 6.6 5.9 8.9 11.8 3.4 4.9 6.1 5.2 8.1 11.7 4.4 7.4 9.3 7.8 12.3 16.7 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. tDLH = Data-to-Pad HIGH 2. tDHL = Data-to-Pad LOW 3. tENZH = Enable-to-Pad, Z to HIGH 4. tENZL = Enable-to-Pad, Z to LOW Output Buffer Delays A A OBx PAD PAD VOL 50% 50% VOH 50% 50% tDLH tDHL Discontinued - v3.0 25 Pr oAS IC (R) 5 0 0 K F a m i l y O u t pu t B uf f e r D e la y s ( W o r st - C a se C om m e r ci al C o nd it i on s , V DDP = 3 .0 V , V D DL = 2 .3 V , T J = 70 C, f C L O CK = 2 5 0 M H z ) Macro Type OB33PH OB33PN OB33PL OB33LH OB33LN OB33LL OB25HH OB25HN OB25HL OB25LH OB25LN OB25LL OB25LPHH OB25LPHN OB25LPHL OB25LPLH OB25LPLN OB25LPLL Description 3.3V, PCI Output Current, High Slew Rate 3.3V, PCI Output Current, Nominal Slew Rate 3.3V, PCI Output Current, Low Slew Rate 3.3V, Low Output Current, High Slew Rate 3.3V, Low Output Current, Nominal Slew Rate 3.3V, Low Output Current, Low Slew Rate 2.5V, High Output Current, High Slew Rate 2.5V, High Output Current, Nominal Slew Rate 2.5V, High Output Current, Low Slew Rate 2.5V, Low Output Current, High Slew Rate 2.5V, Low Output Current, Nominal Slew Rate 2.5V, Low Output Current, Low Slew Rate 2.5V, Low Power, High Output Current, High Slew Rate 2.5V, Low Power, High Output Current, Nominal Slew Rate 2.5V, Low Power, High Output Current, Low Slew Rate 2.5V, Low Power, Low Output Current, High Slew Rate 2.5V, Low Power, Low Output Current, Nominal Slew Rate 2.5V, Low Power, Low Output Current, Low Slew Rate Max. tDLH 4.2 4.7 5.3 6.0 6.7 7.5 6.9 7.2 8.2 10.4 11.0 11.9 5.1 6.0 6.9 7.4 8.6 9.8 Max. tDHL 4.1 5.9 7.1 6.6 9.2 12.1 3.6 5.2 6.4 5.5 8.3 10.9 5.1 7.7 9.8 8.6 12.6 17.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. tDLH = Data-to-Pad HIGH 2. tDHL = Data-to-Pad LOW In p u t B uf fe r D e l a y s VCC PAD PAD IBx Y Y GND tINYH 50% 50% VCC 50% tINYL 0V 50% I n p u t B uf f e r D e l a y s ( W o r st - C a se C om m e r ci al C o nd it i on s , V DDP = 3 .0 V , V D DL = 2 .3 V , T J = 70 C, f C L O CK = 2 5 0 M H z ) Macro Type IB25 IB25LP IB33 Description 2.5V, CMOS Input Levels, No Pull-up Resistor 2.5V, CMOS Input Levels, Low Power 3.3V, CMOS Input Levels, No Pull-up Resistor Max. tINYH 2.2 2.2 1.9 Max. tINYL 0.7 1.4 1.0 Units ns ns ns Notes: 1. tINYH = Input Pad-to-Y HIGH 2. tINYL = Input Pad-to-Y LOW 26 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y G l o b a l I n p ut B u f f e r D el ay s ( W o r st - C a se C om m e r ci al C o nd it io ns , V DDP = 3 .0 V , V D DL = 2 .3 V , T J = 70 C, f C L O CK = 25 0 M H z ) Macro Type GL25 GL25LP GL33 GL25U GL25LPU GL33U Description 2.5V, CMOS Input Levels 2.5V, CMOS Input Levels 3.3V, CMOS Input Levels 2.5V, CMOS Input Levels, with Pull-up Resistor 2.5V, CMOS Input Levels, Low Power, with Pull-up Resistor 3.3V, CMOS Input Levels, with Pull-up Resistor Max. tINYH 2.1 2.3 3.8 2.1 2.3 3.8 Max. tINYL 1.6 2.3 1.2 1.6 2.3 1.2 Units ns ns ns ns ns ns P r e d ic t ed G l ob a l R ou t i ng D el ay * ( W o r st - C a se C om m e r ci al C o nd it io ns , V DDP = 3 .0 V , V D DL = 2 .3 V , T J = 70 C, f C L O CK = 25 0 M H z ) Parameter tRCKH tRCKL tRCKH tRCKL Description Input Low to High (fully loaded row--32 inputs) Input High to Low (fully loaded row--32 inputs) Input Low to High (minimally loaded row--1 input) Input High to Low (minimally loaded row--1 input) Max. 1.2 1.1 0.9 0.9 Units ns ns ns ns * The timing delay difference between tile locations is less than 15ps. G lo b a l R o u t i n g Sk e w ( W o r st - C a se C om m e r ci al C o nd it io ns , V DDP = 3 .0 V , V D DL = 2 .3 V , T J = 70 C, f C L O CK = 25 0 M H z ) Parameter tRCKSWH tRCKSHH Description Maximum Skew Low to High Maximum Skew High to Low Max. 0.3 0.3 Units ns ns M od u l e D e l a y s A B C Y A B C 50% 50% 50% 50% 50% 50% Y 50% 50% 50% 50% 50% 50% tDBLH tDALH tDAHL tDBHL tDCLH tDCHL Discontinued - v3.0 27 Pr oAS IC (R) 5 0 0 K F a m i l y S a m pl e M ac r o ce ll L ib r ar y L is t in g ( W o r st - C a se C om m e r ci al C on di t io n s, V D DL = 2 .3 V , T J = 7 0 C ) Cell Name NAND2 AND2 NOR3 MUX2L OA21 XOR2 LDL DFFL Note: Description 2-Input NAND 2-Input AND 3-Input NOR 2-1 Mux with Active Low Select 2-Input OR into a 2-Input AND 2-Input Exclusive OR Active Low Latch (LH/HL) Negative Edge-Triggered D-type Flip-Flop (LH/HL) Maximum Intrinsic Delay 0.4 0.4 0.4 0.4 0.4 0.3 D: 0.3/0.2 CLK-Q: 0.4/0.4 Minimum Setup/Hold Units ns ns ns ns ns ns tsetup 0.5 thold 0.2 tsetup 0.4 thold 0.2 ns ns Assumes fanout of two. E m b e dd e d M em or y S pe c i f i ca t i o n s This section focuses on the embedded memory of the ProASIC 500K family. It describes the SRAM and FIFO interface signals and includes timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks (Table 4 and Table 5 on page 34). Refer to Table 3 on page 12 for basic RAM configurations. Simultaneous Read and Write to the same location must be done with care. On such accesses the DI bus is output to the DO bus. Enclosed Timing Diagrams--SRAM Mode: Note: * Synchronous RAM Read, Access Timed Output Strobe (Synchronous Transparent) * Synchronous RAM Read, Pipeline Mode Outputs (Synchronous Pipelined) * Asynchronous RAM Write * Asynchronous RAM Read, Address Controlled, RDB=0 * Asynchronous RAM Read, RDB Controlled * Synchronous RAM Write Table 4 * Memory Block SRAM Interface Signals SRAM Signal Bits In/Out Description WCLKS 1 IN RCLKS 1 IN RADDR<0:7> 8 IN RBLKB 1 IN RDB 1 IN WADDR<0:7> 8 IN WBLKB 1 IN DI<0:8> 9 IN WRB 1 IN DO<0:8> 9 OUT RPE 1 OUT WPE 1 OUT PARODD 1 IN Note: Not all signals shown are used in all modes. 28 The difference between synchronous transparent and pipeline modes is the timing of all the output signals from the memory. In transparent mode the outputs will change within the same clock cycle to reflect the data requested by the currently valid access to the memory. However, if clock cycles are short (high clock speed), the data requires most of the clock cycle to change to valid values (stable signals). This makes processing of this data in the same clock cycle nearly impossible. Most designers solve this problem by adding registers at all outputs of the memory to push the data processing into the next clock cycle. In this setup, the whole cycle time can be used to process the data. To simplify the use of this kind of memory setup these registers have been implemented as part of the memory primitive and are available to the user in the synchronous pipeline mode. In this mode, the output signals will change shortly after the second rising edge, following the initiation of the read access. Write clock used on synchronization on write side Read clock used on synchronization on read side Read address Negative true read block select Negative true read pulse Write address Negative true write block select Input data bits <0:8>, <8> can be used for parity in Negative true write pulse Output data bits <0:8>, <8> can be used for parity out Read parity error Write parity error Selects odd parity generation/detect when high, even when low Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y Synchronous RAM Read, Access Timed Output Strobe (Synchronous Transparent) RCLKS Cycle Start RB=(RBD+RBLKB) RADDR New Valid Address DO Old Data Out New Valid Data Out RPE tRACS tRDCS tRDCH tRACH tOCH tRPCH tCMH tOCA tRPCA tCCYC tCML T J = 0 C t o 1 1 0 C ; V DDL = 2 .3 V t o 2 .7 V Symbol txxx CCYC CMH CML OCA OCH RACH RACS RDCH RDCS RPCA RPCH Description Cycle time Clock high phase Clock low phase New DO access from RCLKS Old DO valid from RCLKS RADDR hold from RCLKS RADDR setup to RCLKS RDB hold from RCLKS RDB setup to RCLKS New RPE access from RCLKS Old RPE valid from RCLKS Min. 7.5 3.0 3.0 7.5 Max. Units ns ns ns ns Notes 3.0 0.5 1.0 0.5 1.0 9.5 3.0 ns ns ns ns ns ns ns Discontinued - v3.0 29 Pr oAS IC (R) 5 0 0 K F a m i l y Synchronous RAM Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLKS Cycle Start RB=(RDB+RBLKB) RADDR New Valid Address DO Old Data Out New Valid Data Out RPE Old RPE Out New RPE Out tRACS tRACH tRDCH tRDCS tCMH tCCYC tCML tOCH tRPCA tOCA tRPCH T J = 0 C t o 1 1 0 C ; V DDL = 2 .3 V t o 2. 7V Symbol txxx CCYC CMH CML OCA OCH RACH RACS RDCH RDCS RPCA RPCH Description Cycle time Clock high phase Clock low phase New DO access from RCLKS Old DO valid from RCLKS RADDR hold from RCLKS RADDR setup to RCLKS RDB hold from RCLKS RDB setup to RCLKS New RPE access from RCLKS Old RPE valid from RCLKS Min. 7.5 3.0 3.0 2.0 Max. Units ns ns ns ns Notes .75 0.5 1.0 0.5 1.0 4.0 1.0 ns ns ns ns ns ns ns 30 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y Asynchronous RAM Write WADDR WB=(WRB+WBLKB) DI WPE tAWRS tAWRH tDWRH tWPDA tDWRS tWRML tWRCYC tWRMH tWPDH T J = 0 C t o 1 1 0 C ; V DDL = 2 .3 V t o 2 .7 V Symbol txxx AWRH AWRS DWRH DWRS DWRS WPDA WPDH WRCYC WRMH WRML Description WADDR hold from WB WADDR setup to WB DI hold from WB DI setup to WB DI setup to WB WPE access from DI WPE hold from DI Cycle time WB high phase WB low phase Min. 1.0 0.5 1.5 0.5 2.5 3.0 Max. Units ns ns ns ns ns ns Notes PARGEN is inactive PARGEN is active WPE is invalid while PARGEN is active 1.0 7.5 3.0 3.0 ns ns ns ns Inactive Active Discontinued - v3.0 31 Pr oAS IC (R) 5 0 0 K F a m i l y Asynchronous RAM Read, Address Controlled, RDB=0 RADDR DO RPE tOAH tRPAH tOAA tRPAA tACYC T J = 0 C t o 1 1 0 C ; V DDL = 2 .3 V t o 2. 7V Symbol txxx Description ACYC OAA OAH RPAA RPAH Read cycle time New DO access from RADDR stable Old DO hold from RADDR stable New RPE access from RADDR stable Old RPE hold from RADDR stable Min. 7.5 7.5 Max. Units ns ns Notes 3.0 10.0 3.0 ns ns ns Asynchronous RAM Read, RDB Controlled RB=(RDB+RBLKB) DO RPE tORDH tRPRDH tORDA tRPRDA tRDML tRDCYC T J = 0 C t o 11 0 C ; V DD L = 2. 3V to 2 .7 V tRDMH Symbol txxx ORDA ORDH RDCYC RDMH RDML RPRDA RPRDH Description New DO access from RB Old DO valid from RB Read cycle time RB high phase RB low phase New RPE access from RB Old RPE valid from RB Min. 7.5 Max. 3.0 Units ns ns ns ns ns ns ns Notes 7.5 3.0 3.0 9.5 3.0 Inactive setup to new cycle Active 32 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y Synchronous RAM Write WCLKS Cycle Start WRB, WBLKB WADDR, DI WPE tWRCH, tWBCH tWRCS, tWBCS tDCS, tWDCS tWPCH tDCH, tWACH tWPCA tCMH tCCYC tCML T J = 0 C t o 1 1 0 C ; V DDL = 2 .3 V t o 2 .7 V Symbol txxx CCYC CMH CML DCH DCS WACH WDCS WPCA WPCH WRCH, WBCH WRCS, WBCS Note: Description Cycle time Clock high phase Clock low phase DI hold from WCLKS DI setup to WCLKS WADDR hold from WCLKS WADDR setup to WCLKS New WPE access from WCLKS Old WPE valid from WCLKS WRB & WBLKB hold from WCLKS WRB & WBLKB setup to WCLKS Min. 7.5 3.0 3.0 0.5 1.0 0.5 1.0 3.0 Max. Units ns ns ns ns ns ns ns ns Notes WPE is invalid while PARGEN is active 0.5 0.5 1.0 ns ns ns On simultaneous read and write accesses to the same location DI is output to DO. Discontinued - v3.0 33 Pr oAS IC (R) 5 0 0 K F a m i l y Asynchronous FIFO Full and Empty Transitions The asynchronous FIFO accepts writes and reads while not full or not empty. When the FIFO is full, all writes are inhibited. Conversely, when the FIFO is empty, all reads are inhibited. A problem is created if the FIFO is written during the transition out of full to not full or read during the transition out of empty to not empty. The exact time at which the write (read) operation changes from inhibited to accepted after the read (write) signal which causes the transition from full (empty) to not full (empty) is indeterminate. This indeterminate period starts 1ns after the RB (WB) transition which deactivates full (not empty). For slow cycles, the indeterminate period ends 3ns after the RB (WB) transition. For fast cycles, this period ends either 3ns or (7.5ns - tRDL (tWRL)) after the RB (WB) transition, whichever is later. The timing diagram for write is shown in Figure 19 on page 35. The timing diagram for read is shown in Figure 20 Table 5 * Memory Block FIFO Interface Signals FIFO Signal WCLKS RCLKS LEVEL <0:7> RBLKB RDB RESET WBLKB DI<0:8> WRB FULL, EMPTY EQTH, GEQTH DO<0:8> RPE WPE LGDEP <0:2> PARODD Bits 1 1 8 1 1 1 1 9 1 2 2 9 1 1 3 1 In/Out IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT IN IN Description on page 35. For basic RAM configurations, see Table 3 on page 12. For memory block interface signals, see Table 4 on page 28, and for memory block FIFO signals, see Table 5. Enclosed Timing Diagrams--FIFO Mode: * Asynchronous FIFO Read * Asynchronous FIFO Write * Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) * Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) * Synchronous FIFO Write * FIFO Reset Write clock used to synchronize write side Read clock used to synchronize read side Direct configuration implements static flag logic Active low read block select Active low read pulse Active low reset for FIFO pointers Active low write block select Input data bits <0:8>, <8> can be used for parity in. Active low write pulse FIFO flags. FULL prevents write and EMPTY prevents read EQTH is true when the FIFO holds (LEVEL) words. GEQTH is true when the FIFO holds (LEVEL) words or more Output data bits <0:8>, <8> can be used for parity out. Read parity error Write parity error Configures DEPTH of the FIFO to 2 (LGDEP+1) Selects odd parity generation/detect when high, even when low 34 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y FULL RB Write cycle Write inhibited Write accepted 1ns 3ns WB Figure 19 * Write Timing Diagram EMPTY WB Read cycle Read inhibited Read accepted 1ns 3ns RB Figure 20 * Read Timing Diagram Discontinued - v3.0 35 Pr oAS IC (R) 5 0 0 K F a m i l y Asynchronous FIFO Read Cycle Start RB=(RDB+RBLKB) DO (Empty inhibits read) RPE WB EMPTY FULL EQTH, GETH tRDWRS tORDH tRPRDH tORDA tRPRDA tRDL tRDCYC tRDH tTHRDH tTHRDA tERDH, tFRDH tERDA, tFRDA T J = 0C to 110C; V DDL = 2.3V to 2.7V Symbol txxx ERDH, FRDH, THRDH ERDA FRDA ORDA ORDH RDCYC RDWRS RDH RDL RPRDA RPRDH Description Old EMPTY, FULL, EQTH, & GETH valid hold time from RB New EMPTY access from RB FULL access from RB New DO access from RB Old DO valid from RB Read cycle time WB , clearing EMPTY, setup to RB RB high phase RB low phase New RPE access from RB Old RPE valid from RB Min. Max. 0.5 Units ns Notes Empty/full/thresh are invalid from the end of hold until the new access is complete 3.01 3.01 7.5 3.0 7.5 3.02 1.0 3.0 3.0 9.5 4.0 ns ns ns ns ns ns ns ns ns ns ns ns Enabling the read operation Inhibiting the read operation Inactive Active THRDA EQTH or GETH access from RB 4.5 Notes: 1. At fast cycles, ERDA & FRDA = MAX ((7.5ns - RDL), 3.0ns) 2. At fast cycles, RDWRS (for enabling read) = MAX ((7.5ns - WRL), 3.0ns) 36 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y Asynchronous FIFO Write Cycle Start WB=(WRB+WBLKB) DI (Full inhibits write) WPE RB FULL EMPTY EQTH, GETH tWRRDS tWPDA tDWRS tEWRH, tFWRH tEWRA, tFWRA tTHWRH tTHWRA tWRL tWRCYC tWRH tDWRH tWPDH T J = 0C to 110C; V DDL = 2.3V to 2.7V Symbol txxx DWRH DWRS DWRS EWRH, FWRH, THWRH EWRA FWRA THWRA WPDA WPDH WRCYC WRRDS WRH Description DI hold from WB DI setup to WB DI setup to WB Old EMPTY, FULL, EQTH, & GETH valid hold time after WB EMPTY access from WB New FULL access from WB EQTH or GETH access from WB WPE access from DI WPE hold from DI Cycle time RB , clearing FULL, setup to WB WB high phase Min. 1.5 0.5 2.5 Max. Units ns ns ns Notes PARGEN is inactive PARGEN is active Empty/full/thresh are invalid from the end of hold until the new access is complete 0.5 ns 3.01 3.01 4.5 3.0 1.0 7.5 3.0 2 ns ns ns ns ns ns ns 1.0 ns ns Enabling the write operation Inhibiting the write operation Inactive Active WPE is invalid while PARGEN is active 3.0 WRL WB low phase 3.0 Notes: 1. At fast cycles, EWRA, FWRA = MAX ((7.5ns - WRL), 3.0ns) 2. At fast cycles, WRRDS (for enabling write) = MAX ((7.5ns - RDL), 3.0ns) Discontinued - v3.0 37 Pr oAS IC (R) 5 0 0 K F a m i l y Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) RCLKS Cycle Start RDB DO Old Data Out New Valid Data Out (Empty Inhibits Read) RPE EMPTY FULL EQTH, GETH tRDCH tRDCS tOCH tRPCH tOCA tRPCA tCMH tCCYC tCML tTHCBH tHCBA tECBH, tFCBH tECBA, tFCBA T J = 0C to 110C; V DDL = 2.3V to 2.7V Symbol txxx CCYC CMH CML ECBA FCBA ECBH, FCBH, THCBH OCA OCH RDCH RDCS RPCA RPCH Description Cycle time Clock high phase Clock low phase New EMPTY access from RCLKS FULL access from RCLKS Old EMPTY, FULL, EQTH, & GETH valid hold time from RCLKS New DO access from RCLKS Old DO valid from RCLKS RDB hold from RCLKS RDB setup to RCLKS New RPE access from RCLKS Old RPE valid from RCLKS Min. 7.5 3.0 3.0 3.01 3.01 Max. Units ns ns ns ns ns Notes 1.0 7.5 3.0 0.5 1.0 9.5 3.0 4.5 ns ns ns ns ns ns ns ns Empty/full/thresh are invalid from the end of hold until the new access is complete HCBA EQTH or GETH access from RCLKS Note: 1. At fast cycles, ECBA & FCBA = MAX ((7.5ns - CMH), 3.0ns) 38 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLKS Cycle Start RDB DO Old Data Out New Valid Data Out RPE Old RPE Out New RPE Out EMPTY FULL EQTH, GETH tECBH, tFCBH tRDCH tRDCS tTHCBH tHCBA tRPCA tCMH tCCYC tCML tOCA tECBA, tFCBA tRPCH tOCH T J = 0C to 110C; V DDL = 2.3V to 2.7V Symbol txxx CCYC CMH CML ECBA FCBA ECBH, FCBH, THCBH OCA OCH RDCH RDCS RPCA RPCH Description Cycle time Clock high phase Clock low phase New EMPTY access from RCLKS FULL access from RCLKS Old EMPTY, FULL, EQTH, & GETH valid hold time from RCLKS New DO access from RCLKS Old DO valid from RCLKS RDB hold from RCLKS RDB setup to RCLKS New RPE access from RCLKS Old RPE valid from RCLKS Min. 7.5 3.0 3.0 3.01 3.01 Max. Units ns ns ns ns ns Notes 1.0 ns Empty/full/thresh are invalid from the end of hold until the new access is complete 2.0 0.75 0.5 1.0 4.0 1.0 4.5 ns ns ns ns ns ns ns HCBA EQTH or GETH access from RCLKS Note: 1. At fast cycles, ECBA & FCBA = MAX ((7.5ns - CMS), 3.0ns) Discontinued - v3.0 39 Pr oAS IC (R) 5 0 0 K F a m i l y Synchronous FIFO Write WCLKS Cycle Start WRB, WBLKB (Full Inhibits Write) DI WPE FULL EMPTY EQTH, GETH tWRCH, tWBCH tWRCS, tWBCS tDCS tWPCH tDCH tWPCA tCMH tCCYC tCML tHCBA tECBH, tFCBH tECBA, tFCBA tHCBH T J = 0C to 110C; V DDL = 2.3V to 2.7V Symbol txxx CCYC CMH CML DCH DCS FCBA ECBA ECBH, FCBH, HCBH HCBA WPCA WPCH WRCH, WBCH Cycle time Description Min. 7.5 3.0 3.0 0.5 1.0 3.01 3.01 Max. Units ns ns ns ns ns ns ns Notes Clock high phase Clock low phase DI hold from WCLKS DI setup to WCLKS New FULL access from WCLKS EMPTY access from WCLKS Old EMPTY, FULL, EQTH, & GETH valid hold time from WCLKS EQTH or GETH access from WCLKS New WPE access from WCLKS Old WPE valid from WCLKS WRB & WBLKB hold from WCLKS 1.0 ns Empty/full/thresh are invalid from the end of hold until the new access is complete WPE is invalid while PARGEN is active 4.5 3.0 0.5 0.5 1.0 ns ns ns ns ns WRCS, WRB & WBLKB setup to WCLKS WBCS Note: 1. At fast cycles, ECBA & FCBA = MAX ((7.5ns - CMH), 3.0ns) 40 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y FIFO Reset RESETB WRB, WBLKB Cycle Start WCLKS, RCLKS Cycle Start FULL EMPTY EQTH, GETH tCBRSS tERSA, tFRSA tTHRSA tRSL tWBRSS tCBRSH tWBRSH T J = 0 C t o 1 1 0 C ; V DDL = 2 .3 V t o 2 .7 V Symbol txxx CBRSH CBRSS ERSA FRSA RSL THRSA WBRSH WBRSS Description WCLKS or RCLKS hold from RESETB WCLKS or RCLKS setup to RESETB New EMPTY access from RESETB FULL access from RESETB RESETB low phase EQTH or GETH access from RESETB WB hold from RESETB WB setup to RESETB Min. 1.5 1.5 3.0 3.0 7.5 4.5 1.5 1.5 Max. Units ns ns ns ns ns ns ns ns Notes Synchronous mode only Synchronous mode only Asynchronous mode only Asynchronous mode only Discontinued - v3.0 41 Pr oAS IC (R) 5 0 0 K F a m i l y P i n D e s c r i p ti o n I/O User Input/Output V PN Programming Supply Pin The I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output signal levels are compatible with standard LVTTL and LVCMOS specifications. Unused I/O pins are configured as inputs with pull-up resistors. N/C No Connect This pin must be connected to GND during normal operation, or it can remain at -12V in an ISP application. This pin must not float. TMS Test Mode Select The TMS pin controls the use of Boundary Scan circuitry. TCK Test Clock To maintain compatibility with future Actel ProASIC products it is recommended that this pin not be connected to the circuitry on the board. GL Global Input Pin Clock input pin for Boundary Scan. TDI Test Data In Serial input for Boundary Scan. TDO Test Data Out Low skew input pin for clock or other global signals. Input only. This pin can be configured with a pull-up resistor. GND Ground Serial output for Boundary Scan. TRST Test Reset Input Common ground supply voltage. V DDL Logic Array Power Supply Pin Asynchronous, active low input pin for resetting Boundary Scan circuitry. RCK Running Clock 2.5V supply voltage. V DDP I/O Pad Power Supply Pin 2.5V or 3.3V supply voltage. V PP Programming Supply Pin A free running clock is needed during programming if the programmer cannot guarantee that TCK will be uninterrupted. This pin must be connected to VDDP during normal operation, or it can remain at 16.5V in an ISP application. This pin must not float. 42 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y P a ck a g e Pi n A s s i g nm en t s 20 8 -P in P Q F P 208 1 208-Pin PQFP Discontinued - v3.0 43 Pr oAS IC (R) 5 0 0 K F a m i l y 20 8 -P in P Q F P Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 A500K050 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL GND I/O I/O I/O I/O VDDP I/O I/O GL GL I/O I/O GND I/O I/O I/O I/O I/O I/O VDDL I/O I/O I/O VDDP GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND A500K130 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL GND I/O I/O I/O I/O VDDP I/O I/O GL GL I/O I/O GND I/O I/O I/O I/O I/O I/O VDDL I/O I/O I/O VDDP GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND A500K180 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL GND I/O I/O I/O I/O VDDP I/O I/O GL GL I/O I/O GND I/O I/O I/O I/O I/O I/O VDDL I/O I/O I/O VDDP GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND A500K270 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL GND I/O I/O I/O I/O VDDP I/O I/O GL GL I/O I/O GND I/O I/O I/O I/O I/O I/O VDDL I/O I/O I/O VDDP GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND Pin Number 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 A500K050 Function VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VDDL VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VDDL VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP A500K130 Function VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VDDL VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VDDL VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP A500K180 Function VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VDDL VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VDDL VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP A500K270 Function VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VDDL VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VDDL VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCKO TDI TMS VDDP 44 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y 20 8 -P in P Q F P ( C on t in u ed ) Pin Number 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 A500K050 Function GND VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDDL I/O I/O I/O GND I/O I/O GL GL I/O I/O I/O VDDP I/O I/O GND VDDL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND A500K130 Function GND VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDDL I/O I/O I/O GND I/O I/O GL GL I/O I/O I/O VDDP I/O I/O GND VDDL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND A500K180 Function GND VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDDL I/O I/O I/O GND I/O I/O GL GL I/O I/O I/O VDDP I/O I/O GND VDDL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND A500K270 Function GND VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDDL I/O I/O I/O GND I/O I/O GL GL I/O I/O I/O VDDP I/O I/O GND VDDL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND Pin Number 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 A500K050 Function VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDDL I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDDL I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP A500K130 Function VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDDL I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDDL I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP A500K180 Function VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDDL I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDDL I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP A500K270 Function VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDDL I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDDL I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP Discontinued - v3.0 45 Pr oAS IC (R) 5 0 0 K F a m i l y P ac k a g e Pi n A s s i g nm en t s (Continued) 27 2 -P in P B G A ( B o t t o m V ie w ) 20 19 18 17 16 15 14 13 12 11 10 9 A B C D E F G H J K L M N P R T U V W Y 8 7 6 5 4 3 2 1 46 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y 2 7 2 -P in P B G A Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 A500K050 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A500K130 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 A500K050 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP I/O VDDL VDDL VDDL VDDL VDDL VDDL I/O VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O VDDP A500K130 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP I/O VDDL VDDL VDDL VDDL VDDL VDDL I/O VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O VDDP Pin Number F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J9 J10 J11 J12 J17 J18 J19 J20 K1 K2 K3 K4 K9 K10 K11 K12 K17 K18 K19 K20 L1 L2 A500K050 Function VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GL I/O GL GL VDDL GND GND GND GND VDDL GL I/O I/O I/O I/O I/O VDDL GND GND GND GND VDDL I/O I/O I/O I/O I/O A500K130 Function VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GL I/O GL GL VDDL GND GND GND GND VDDL GL I/O I/O I/O I/O I/O VDDL GND GND GND GND VDDL I/O I/O I/O I/O I/O Discontinued - v3.0 47 Pr oAS IC (R) 5 0 0 K F a m i l y 27 2 -P in P B G A ( C o nt in ue d ) Pin Number L3 L4 L9 L10 L11 L12 L17 L18 L19 L20 M1 M2 M3 M4 M9 M10 M11 M12 M17 M18 M19 M20 N1 N2 N3 N4 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 A500K050 Function I/O VDDL GND GND GND GND VDDL I/O I/O I/O I/O I/O I/O VDDL GND GND GND GND VDDL I/O I/O I/O I/O I/O I/O VDDL VDDL I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O A500K130 Function I/O VDDL GND GND GND GND VDDL I/O I/O I/O I/O I/O I/O VDDL GND GND GND GND VDDL I/O I/O I/O I/O I/O I/O VDDL VDDL I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O Pin Number T1 T2 T3 T4 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 A500K050 Function I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP I/O VDDL VDDL VDDL VDDL VDDL VDDL I/O VDDP VDDP VDDP RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO A500K130 Function I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP I/O VDDL VDDL VDDL VDDL VDDL VDDL I/O VDDP VDDP VDDP RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO Pin Number V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 A500K050 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN I/O A500K130 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN I/O 48 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y P a ck a g e Pi n A s s i g nm en t s (Continued) 4 5 6 -P in P B G A ( B o t t o m V i e w ) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 8 7 6 5 4 3 2 1 Discontinued - v3.0 49 Pr oAS IC (R) 5 0 0 K F a m i l y 4 5 6 -P in P B G A Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 A500K130 Function VDDP VDDP NC I/O I/O NC I/O NC NC I/O NC NC I/O NC NC I/O NC NC I/O NC NC I/O NC NC VDDP VDDP I/O I/O I/O I/O VDDL VDDL I/O I/O I/O NC NC I/O I/O I/O VDDL VDDL VDDL I/O I/O I/O A500K180 Function VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O VDDL VDDL I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL VDDL I/O I/O I/O A500K270 Function VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O VDDL VDDL I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL VDDL I/O I/O I/O Pin Number AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 A500K130 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL VDDL I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO VDDP RCK I/O NC NC I/O VDDP I/O A500K180 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL VDDL I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO VDDP RCK I/O I/O I/O I/O VDDP I/O A500K270 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL VDDL I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO VDDP RCK I/O I/O I/O I/O VDDP I/O 50 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y 45 6 -P in P B G A ( C o n t in ue d ) Pin Number AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 A500K130 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP I/O VDDP I/O NC VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VPN TRST A500K180 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP I/O VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VPN TRST A500K270 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP I/O VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VPN TRST Pin Number AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 A500K130 Function VDDP VDDP VDDP VDDP NC NC I/O NC NC I/O NC NC I/O NC NC I/O NC NC I/O NC NC I/O NC I/O TDI NC VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A500K180 Function VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A500K270 Function VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Discontinued - v3.0 51 Pr oAS IC (R) 5 0 0 K F a m i l y 45 6 -P in P B G A ( C o nt in ue d ) Pin Number B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 A500K130 Function I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O NC NC I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O A500K180 Function I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O A500K270 Function I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O Pin Number D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 A500K130 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O NC I/O I/O I/O VDDL VDDL VDDL VDDL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL VDDL I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL A500K180 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O VDDL VDDL VDDL VDDL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL VDDL I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL A500K270 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O VDDL VDDL VDDL VDDL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL VDDL I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL 52 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y 45 6 -P in P B G A ( C o n t in ue d ) Pin Number F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 A500K130 Function I/O I/O I/O NC NC I/O I/O I/O VDDL VDDL I/O I/O I/O I/O NC I/O I/O I/O VDDL VDDL I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O A500K180 Function I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A500K270 Function I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number L3 L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M11 M12 M13 M14 M15 M16 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N11 N12 N13 N14 N15 N16 N22 N23 N24 N25 N26 A500K130 Function I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O NC GL GL I/O I/O I/O GND GND GND GND GND GND GL I/O I/O I/O NC NC I/O I/O I/O I/O GND GND GND GND GND GND I/O GL I/O I/O I/O A500K180 Function I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O GL GL I/O I/O I/O GND GND GND GND GND GND GL I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O GL I/O I/O I/O A500K270 Function I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O GL GL I/O I/O I/O GND GND GND GND GND GND GL I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O GL I/O I/O I/O Discontinued - v3.0 53 Pr oAS IC (R) 5 0 0 K F a m i l y 45 6 -P in P B G A ( C o nt in ue d ) Pin Number P1 P2 P3 P4 P5 P11 P12 P13 P14 P15 P16 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R11 R12 R13 R14 R15 R16 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15 T16 T22 A500K130 Function NC I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O NC I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O NC NC I/O I/O I/O I/O GND GND GND GND GND GND I/O A500K180 Function I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O A500K270 Function I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O Pin Number T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 A500K130 Function I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O VDDL VDDL I/O I/O I/O I/O NC I/O I/O I/O VDDL VDDL I/O I/O I/O NC A500K180 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL I/O I/O I/O I/O A500K270 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL I/O I/O I/O I/O 54 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y P a ck a g e A s s i g nm en t s (Continued) 14 4 -F B G A ( B ot t o m V ie w ) A1 Ball Pad Corner 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M Discontinued - v3.0 55 Pr oAS IC (R) 5 0 0 K F a m i l y 14 4 -p in F B G A Pin Number A500K050 Function A500K130 Function Pin Number A500K050 Function A500K130 Function Pin Number A500K050 Function A500K130 Function A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 I/O I/O I/O I/O I/O GND I/O VDDL I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GL I/O VDDL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VDDL I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GL I/O VDDL I/O I/O I/O I/O I/O I/O I/O I/O D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL I/O I/O VDDP I/O VDDP VDDP I/O VDDP VDDL I/O I/O GL I/O I/O I/O GND GND GND I/O GL GND I/O GL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL I/O I/O VDDP I/O VDDP VDDP I/O VDDP VDDL I/O I/O GL I/O I/O I/O GND GND GND I/O GL GND I/O GL G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 I/O GND I/O I/O GND GND GND I/O I/O I/O I/O I/O VDDL I/O I/O I/O VDDL I/O I/O I/O I/O VDDP I/O VDDL I/O I/O VDDP I/O I/O I/O VDDL TCK I/O TDO I/O I/O I/O GND I/O I/O GND GND GND I/O I/O I/O I/O I/O VDDL I/O I/O I/O VDDL I/O I/O I/O I/O VDDP I/O VDDL I/O I/O VDDP I/O I/O I/O VDDL TCK I/O TDO I/O I/O 56 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y 14 4 -p in F B G A ( C on t in u ed ) Pin Number A500K050 Function A500K130 Function Pin Number A500K050 Function A500K130 Function Pin Number A500K050 Function A500K130 Function K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 GND I/O I/O I/O VDDP I/O I/O I/O TMS RCK I/O TRST GND I/O I/O I/O VDDP I/O I/O I/O TMS RCK I/O TRST M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 I/O I/O I/O I/O I/O I/O I/O I/O TDI VDDP VPP VPN I/O I/O I/O I/O I/O I/O I/O I/O TDI VDDP VPP VPN Discontinued - v3.0 57 Pr oAS IC (R) 5 0 0 K F a m i l y P ac k a g e A s s i g nm en t s (Continued) 25 6 -F B G A ( B ot t o m V ie w) A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7654 321 A B C D E F G H J K L M N P R T 58 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y 25 6 -p in F B G A Pin Number A500K130 Function A500K180 Function A500K270 Function Pin Number A500K130 Function A500K180 Function A500K270 Function A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O Discontinued - v3.0 59 Pr oAS IC (R) 5 0 0 K F a m i l y 25 6 -p in F B G A ( C on t in u ed ) Pin Number A500K130 Function A500K180 Function A500K270 Function Pin Number A500K130 Function A500K180 Function A500K270 Function E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 I/O I/O I/O I/O I/O I/O VDDP GND VDDL VDDL VDDL VDDL GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDL GND GND GND GND VDDL VDDP I/O I/O I/O I/O GL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDDL VDDL VDDL VDDL GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDL GND GND GND GND VDDL VDDP I/O I/O I/O I/O GL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDDL VDDL VDDL VDDL GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDL GND GND GND GND VDDL VDDP I/O I/O I/O I/O GL I/O I/O I/O I/O H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 VDDL GND GND GND GND VDDL I/O I/O I/O I/O GL GL I/O I/O I/O I/O VDDL GND GND GND GND VDDL I/O I/O I/O I/O GL I/O I/O I/O I/O VDDP VDDL GND GND GND GND VDDL VDDP VDDL GND GND GND GND VDDL I/O I/O I/O I/O GL GL I/O I/O I/O I/O VDDL GND GND GND GND VDDL I/O I/O I/O I/O GL I/O I/O I/O I/O VDDP VDDL GND GND GND GND VDDL VDDP VDDL GND GND GND GND VDDL I/O I/O I/O I/O GL GL I/O I/O I/O I/O VDDL GND GND GND GND VDDL I/O I/O I/O I/O GL I/O I/O I/O I/O VDDP VDDL GND GND GND GND VDDL VDDP 60 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y 25 6 -p in F B G A ( C on t in u ed ) Pin Number A500K130 Function A500K180 Function A500K270 Function Pin Number A500K130 Function A500K180 Function A500K270 Function K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDDL VDDL VDDL VDDL GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDDL VDDL VDDL VDDL GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDDL VDDL VDDL VDDL GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Discontinued - v3.0 61 Pr oAS IC (R) 5 0 0 K F a m i l y 25 6 -p in F B G A ( C on t in u ed ) Pin Number A500K130 Function A500K180 Function A500K270 Function Pin Number A500K130 Function A500K180 Function A500K270 Function R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 I/O I/O I/O TDI VPN TDO GND I/O I/O I/O I/O I/O I/O I/O TDI VPN TDO GND I/O I/O I/O I/O I/O I/O I/O TDI VPN TDO GND I/O I/O I/O I/O T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS GND I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS GND I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS GND 62 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y P a ck a g e A s s i g nm en t s (Continued) 67 6 -p in F B G A ( B ot t o m V ie w ) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 8 7 6 5 4 3 2 1 Discontinued - v3.0 63 Pr oAS IC (R) 5 0 0 K F a m i l y 6 7 6 -P in F B G A Pin Number A500K270 Function Pin Number A500K270 Function Pin Number A500K270 Function Pin Number A500K270 Function Pin Number A500K270 Function A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 I/O I/O I/O I/O I/O I/O I/O I/O TDO GND GND I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK TRST I/O I/O AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 B1 B2 B3 B4 B5 B6 B7 B8 I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O 64 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y 67 6 -P in F B G A ( C o n t in ue d ) Pin Number A500K270 Function Pin Number A500K270 Function Pin Number A500K270 Function Pin Number A500K270 Function Pin Number A500K270 Function B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G20 G19 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL NC NC NC NC NC NC NC NC NC NC NC VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 I/O I/O VDDP VDDL VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDL VDDL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL Discontinued - v3.0 65 Pr oAS IC (R) 5 0 0 K F a m i l y 67 6 -P in FB G A ( C o n t in ue d ) Pin Number A500K270 Function Pin Number A500K270 Function Pin Number A500K270 Function Pin Number A500K270 Function Pin Number A500K270 Function J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 L1 L2 VDDL VDDL VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDDL GND GND GND GND GND GND GND GND VDDL VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 I/O I/O I/O I/O NC VDDP VDDL GND GND GND GND GND GND GND GND VDDL VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDDL GND GND GND GND GND M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 GND GND GND VDDL VDDP NC I/O I/O I/O I/O I/O I/O GL I/O I/O I/O I/O I/O NC VDDP VDDL GND GND GND GND GND GND GND GND VDDL VDDP NC I/O GL I/O I/O GL I/O P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 GL I/O I/O I/O I/O I/O NC VDDP VDDL GND GND GND GND GND GND GND GND VDDL VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDDL GND GND GND R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 GND GND GND GND GND VDDL VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDDL GND GND GND GND GND GND GND GND VDDL VDDP NC I/O I/O I/O I/O 66 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y 67 6 -P in F B G A ( C o n t in ue d ) Pin Number A500K270 Function Pin Number A500K270 Function Pin Number A500K270 Function Pin Number A500K270 Function Pin Number A500K270 Function T25 T26 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDDL GND GND GND GND GND GND GND GND VDDL VDDP U20 U21 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDDL VDDL VDDL VDDL VDDL VDDL V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W6 W7 W8 W9 VDDL VDDL VDDL VDDL VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDL VDDL VDDP W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDL VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 I/O I/O I/O VDDP NC NC NC NC NC NC NC NC NC NC VDDL VPP I/O I/O I/O I/O I/O I/O Discontinued - v3.0 67 Pr oAS IC (R) 5 0 0 K F a m i l y L i s t o f C ha n g es The following table lists critical changes that were made in the current version of the document. Previous version v2.0 Changes in current version (v3.0) WDATA has been changed to DI, and RDATA has been changed to DO to make them consistent with the signal names found in the Macro Library Guide. The "Product Plan" on page 3 has been updated to include the 256-FBGA package. The "Plastic Device Resources" on page 3 has been updated to include the 256-FBGA package. Figure 12 and Figure 13 on page 13 have been updated. The "Design Environment" on page 15 and Figure 17 on page 15 have been updated. Package Thermal Characteristics table on page 16 has been updated to include the 256-FBGA package. The "Calculating Power Dissipation" on page 17 has been changed. The "Programming and Storage Temperature LImits" on page 18 is new. The "DC Electrical Specifications (VDDP = 2.5V)" on page 19 has been updated. The "DC Electrical Specifications (VDDP = 3.3V)" on page 20 has been updated. The Table 4 on page 28 has been updated. The Table 5 on page 34 has been updated. The "256-FBGA (Bottom View)" on page 58 is new. Preliminary v1.0 In the "676-pin FBGA (Bottom View)" on page 63, the functions for pins N1, N22, N25, and P1 have changed from I/O to GL The section, "Clock Trees" on page 8 is new. The table, "DC Electrical Specifications (VDDP = 3.3V)" on page 20 is new. The table, "AC Specifications (3.3V PCI Operation)" on page 22 is new. The table, the "Slew Rates Measured at Cout = 10pF (Total Output Load), Nominal Power Supplies and 25C" on page 24 is new. The numbers found in the "Tristate Buffer Delays (Worst-Case Commercial Conditions, VDDP = 3.0V, VDDL = 2.3V, TJ = 70C, fCLOCK = 250 MHz)" on page 25 have changed. Advanced v.4 The numbers found in the "Output Buffer Delays (Worst-Case Commercial Conditions, VDDP = 3.0V, VDDL = 2.3V, TJ = 70C, fCLOCK = 250 MHz)" on page 26 have changed. page 3 page 3 page 13 page 15 page 16 page 17 page 18 page 19 page 20 page 28 page 34 page 58 page 59 page 8 page 18 page 20 page 22 Page Preliminary v1.1 page 23 page 24 The numbers found in the "Input Buffer Delays (Worst-Case Commercial Conditions, VDDP = 3.0V, VDDL = 2.3V, TJ = 70C, fCLOCK = 250 MHz)" on page 26 have page 24 changed. The numbers found in the "Global Input Buffer Delays (Worst-Case Commercial Conditions, VDDP = 3.0V, VDDL = 2.3V, TJ = 70C, fCLOCK = 250 MHz)" on page 27 have changed. The "144-FBGA (Bottom View)" on page 55 for A500K050 is new. The "676-pin FBGA (Bottom View)" on page 63 for A500K130 and A500K270 are new. page 25 pages 53-55 pages 56-60 68 Discontinued - v3.0 Pr oAS IC (R) 5 0 0 K F a m i l y D a ta S h e e t C at e g or i e s In order to provide the latest information to designers, some data sheets are published before data has been fully characterized. These data sheets are marked as "Advanced" or Preliminary" data sheets. The definition of these categories are as follows: Advanced The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. P r e li mi na r y The data sheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. U n m a r k e d ( pr o d u c t i o n ) The data sheet contains information that is considered to be final. W eb -o n l y V e r s i o n s Web-only versions have three numbers in the version number (example: v2.0.1). A web-only version means Actel is posting the data sheet so customers have the latest information, but we are not printing the version because some information is going to change shortly after posting. Discontinued - v3.0 69 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Europe Ltd. Maxfli Court, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Tel: +44 (0)1276 401450 Fax: +44 (0)1276 401490 Actel Corporation 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Asia-Pacific EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81 03-3445-7671 Fax: +81 03-3445-7668 5172140-7/2.02 |
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